RTL is a simple, human-oriented language to specify the operations, register communication and timing of the steps that take place within a CPU to carry out higher level (user programmable) instructions.
Micro-operations can be expressed in terms of a Register Transfer Language (RTL).
Register Transfer: Register Transfer can be denoted by the following way:
Here content of Register R1 gets transferred to Register R2.
Conditional Register Transfer: Conditions in Register Transfer simply depict that the transfer takes place only when the appropriate condition becomes TRUE. It can be denoted by the following way:
Registers are shown like a horizontal row with many blocks in between. The blocks are counted from right to left. In an n-bit register, the right most block is called LSB (Least Significant Bit) and represented as 0th while the left most bit is called MSB (Most Significant Bit) and represented as (n-1)th. Consider the following diagrams of an 8-bit register R1 -
It is a conditional operation, Here, Two register operations:
are being performed simultaneously when T input equals to “1”.