Flip Flops:- A Flip-Flop is a basic electronic circuit that is designed to store a single bit either it is a â€œ0â€� or a â€œ1â€�. Thus we can say that a Flip-
Flop is the smallest unit of an Electronic Memory. Flip-Flops are of a major importance to computer architecture but before we
proceed onto the topic, we must understand a LATCH. Latch:-A Latch is a circuit that incorporates two basic NOR or NAND gates in a CROSS-COUPLED connection. This peculiar
connection is necessary because the aim is to create a locking system that will be able to lock a single bit in it. RS Latch with NOR Gate:-
SR Latch with NAND Gate:-
Note: A Latch is designed to have two outputs- one is Q while other is Qâ€™. Here Q is regarded as the actual output while Qâ€™ is simply to
balance the output. For a Latch, to work properly, Qâ€™ should always be compliment of Q. Here in both of these truth tables, when
S=R=1; both Q and Qâ€™ tend to be 1 which is logically not allowed. Flip Flops
A Flip-Flop is nothing but a clocked Latch circuit. Since we use a clock input signal, this circuit becomes able to generate different
outputs in different clock periods.
Normally a clock input is either â€œ0â€� or â€œ1â€�, hence the Flip-Flop is often called as a TWO STATE MULTIVIBRATOR or
Depending upon design, usage and technology, Flip-Flops are categorized into several types. Some of these are listed here:
SR (Set-Reset) Flip-Flop:
As its name implies, the SR Flip-Flop works for just two states. Either it SETs (stores 1 to the Latch) or it RESETs (stores 0 to the
Latch). Although a Flip-Flop can be constructed by any of the two types of Latches, but the best practice is to use NAND gate
D (Data) Flip-Flop:
D Flip-Flop is a slight modification of SR Flip-Flop. Since SR flip flop suffers from an unavoidable condition called NO VALUE
or RACE CONDITION. D Flip-Flop is designed to avoid it. The D input to this Flip-Flop is sole input and is inverted to create a
set of two necessary inputs. This management disables the similar input combinations like [0,0] or [1,1] and only SET, RESET
outputs are evaluated.
JK (Jack Kilby) Flip-Flop:
The JK flip-flop is basically an SR flip-flop with feedback which enables only one of its two input terminals, either SET or RESET
to be active at any one time thereby eliminating the RACE CONDITION seen previously in the SR flip flop circuit. Also when
both the J and the K inputs are at logic level â€œ1â€� at the same time, and the clock input is pulsed either â€œHIGHâ€�, the circuit will
â€œtoggleâ€� from its SET state to a RESET state, or visa-versa.
T (Toggling) Flip-Flop:
T Flip-Flop is a slight modification of JK Flip-Flop. The T input to this Flip-Flop is sole input and is distributed to create a set of
two necessary inputs. This management disables the differing input combinations like [0,1] or [1,0] and only â€œNO CHANGEâ€� &
â€œTOGGLEâ€� outputs are evaluated.
Edge-Triggering is nothing but a technology through which at least two Flip-Flops can be connected to work on different clock
pulses respectively. The First Flip-Flop that gets normal Clock pulse is called a MASTER FLIP-FLOP while the other getting
inverted Clock pulse is called a SLAVE FLIP-FLOP. This entire combination is often termed as MASTER-SLAVE FLIP-FLOP. Block Diagram: