The external clock pulses (pulses to be counted) are fed directly to each of the J-K flip-flops in the counter chain and both the J and K inputs are all tied together in toggle mode, but only in the first flip-flop, logic is set to “1” allowing the flip-flop to toggle on every clock pulse. Then the synchronous counter follows a predetermined sequence of states in response to the common clock signal, advancing one state for each pulse.
Following is a diagram that clearly shows the TOGGLING effect of JK Flip-Flop on this counter. We can see that the Right most Flip-Flop works as for LSB bit while the Left most bit works as for the MSB bit. Thus Q3 toggles every-time when FF3 sets to 1. Q2 toggles every-time when FF2 sets to 1 and so on.